1. Field of the Invention
The present invention relates to an image sensor and, more specifically, to an image sensor in which an amplifier circuit is provided to each pixel.
2. Description of the Related Art
The techniques for inspecting the inside of an examination target by nondestructive testing using X-ray transmission images are essential techniques in the fields of medical and industrial nondestructive testing. In particular, an X-ray image sensor which directly captures X-ray transmission images as electronic data has become broadly employed since it is rapid in capturing images, capable of assisting image reading by performing image processing, capable of handling moving images, etc. Mainly used as the X-ray image sensor is a device called FPD (Flat Panel Detector). In the FPD, each of two-dimensionally disposed pixels is provided with: a photoelectric conversion section which converts the X-ray into an electric charge; and a switching element which takes out signal electric charges accumulated in the photoelectric conversion section to the outside. The FPD is fabricated by using a thin film semiconductor technique on a large-area substrate such as glass. It is because an X-ray reduction optical system cannot be fabricated easily unlike the case of visible light, so that the size of the FPD is required to be in a same size as that of the examination target or larger. Thus, as the switching element disposed at the pixel, a TFT (Thin Film Transistor) is used.
The FPD can be roughly classified into two kinds depending on the systems for converting the X-ray into electric charges. One is an indirect conversion system which converts the X-ray into visible light, and the visible light is converted into electric charges. The other one is a direct conversion type which converts the X-ray into electric charges directly.
As the indirect conversion type FPD, there is a structure disclosed in FIG. 5 of Japanese Unexamined Patent Publication Hei 04-206573 (Patent Document 1). In this structure, a phosphor is stacked via an insulating film on a part where a photodiode and a transistor are formed. The phosphor layer emits visible light by irradiation of X-ray, and the photodiode converts the visible light into an electric charge. Further, the technique of Patent Document 1 discloses a case of forming the photodiode and the transistor with a-Si (amorphous silicon).
As the direct conversion type FPD, there is a structure disclosed in FIG. 1 of Japanese Unexamined Patent Publication Hei 11-211832 (Patent Document 2). In this structure, a pixel formed by connecting a photoconductive layer to a transistor is formed on a substrate. X-ray is absorbed by the photoconductive layer and directly converted into an electric charge. The technique of Patent Document 2 discloses a method which uses ZnO, CdS, CdSe, or the like as the photoconductive layer.
Signals in the FPD of the both types are outputted as the electric charges, which are converted into voltages by a signal detection circuit such as an external integrator and digitalized. The techniques of Patent Documents 1 and 2 shown herein output the signal electric charges themselves acquired by each pixel, so that those may be classified as PPS (Passive Pixel Sensor) in some cases because the signal electric charges are not amplified within the pixels with those techniques.
Recently, in the field of medical treatment, it has become strongly desired to decrease exposure to radiation and achieve high definition for the X-ray diagnosis devices. When the X-ray irradiation amount is decreased for decreasing the exposure to radiation, the signal electric charges detected by the FPD is decreased so that the S/N ratio is deteriorated. Further, when the pixel size of the FPD is designed to be small for achieving high definition, the signal electric charge is also decreased accordingly. Therefore, the S/N ratio is deteriorated. That is, in order to achieve both low exposure to radiation and high definition, it is essential to increase the S/N ratio of the FPD.
As the way of increasing the S/N ratio of the image sensor, there is a technique called APS (Active Pixel Sensor) which is employed for CMOS image sensors. It is a technique with which an amplifier circuit is provided to each pixel of an image sensor in addition to a photoelectric conversion element such as a photodiode to amplify and output the signals of the photoelectric conversion element. This technique makes it possible to improve the S/N ratio of the signals greatly compared to the case of the PPS type.
The CMOS image sensor is normally integrated on a monocrystalline Si substrate and mainly used for an optical camera or the like, and the APS technique has been tried to be employed for thin film transistors. As examples thereof, there are the techniques disclosed in Japanese Unexamined Patent Publication Sho 58-068968 (Patent Document 3 (FIG. 1)) and Japanese Unexamined Patent Publication Sho 60-091666 (Patent Document 4 (FIG. 2)). The technique disclosed in Patent Document 3 is a case where a polycrystalline Si TFT is used as a transistor for amplifying the signal. The technique disclosed in Patent Document 4 is a case where an a-Si TFT is used as a transistor for amplifying the signal.
Actually, however, the APS image sensors using the polycrystalline Si TFT or the a-Si TFT are hardly put into practical use. Reasons thereof will be described hereinafter.
In the case of using the polycrystalline Si TFT, variation in the threshold voltage is extremely large. The variation in the characteristic is a substantial problem caused by variation in the crystalline particle diameter of the polycrystalline Si. When there is variation generated in the threshold voltage of the TFTs constituting the amplifier circuits, there is also variation generated in the output voltage of the amplifier circuits. The variation in the threshold voltage is significant between the TFT elements disposed extremely close to each other, so that it is difficult to eliminate it by devising the circuits. Thus, when the amplifier circuit of the polycrystalline Si TFT is provided to each pixel of the image sensor, there is variation generated in the signals in each of the pixels, thereby generating FPN (Fixed Pattern Noise).
In a case where the a-Si TFT is used for amplifying the signals, the issue of variation in the threshold voltage caused due to the crystalline structure like the case of the polycrystalline Si TFT does not occur due to its amorphous structure. However, there is an issue generated in terms of the reliability, and it is a phenomenon where the threshold voltage fluctuates greatly when a voltage is continuously applied between the gate and the source with the a-Si TFT. With the TFT used for the amplifier circuit, a voltage for making the TFT electrically connected at all times is continuously applied between the gate and the source. Thus, the threshold voltage of the TFT used for the amplifier circuit fluctuates, so that the output voltage also fluctuates accordingly. The issue regarding the reliability is also generated with the TFT using an amorphous oxide semiconductor.
The fluctuation amount of the threshold voltage of the a-Si TFT, the amorphous oxide semiconductor TFT, and the like depends on the extent and the time of the voltage applied between the gate and source of the TFT. Thus, it is considered to suppress the fluctuation in the threshold voltage through controlling the voltage applied between the source and the gate to be small and to shorten the applying time.
Even though it is not targeted to overcome the above-described issue regarding the reliability of the TFT, Japanese Unexamined Patent Publication 2010-098714 (Patent Document 5 (FIG. 1, FIG. 2)) discloses a technique for altering the gate voltage of the TFT to be the amplifier circuit in the image sensor that employs the APS technique.
FIG. 16 shows the circuit structure of the image sensor disclosed in Patent Document 5 as Related Art 1. With Related Art 1, each pixel 900 of the image sensor is provided with: a transistor 901 to be the amplifier circuit; a photodiode 902, a storage capacitance 903, and a reset transistor 904.
A first terminal 951 of a current source 905 that is the load for the transistor 901 is connected to an output wiring DATA that is common to each pixel sequence. Regarding the photodiode 902, an anode terminal 92a is connected to a control line RSEL, and a cathode terminal 92k is connected to a gate terminal 91g of the transistor 901 and a source terminal 94s of the transistor 904. The storage capacitance 903 is connected in parallel to the photodiode 902. Regarding the transistor 901, a drain terminal 91d is connected to a power source line P91 (power source voltage VDD), and a source terminal 91s is connected to the output wiring DATA. Regarding the transistor 904, a gate terminal 94g is connected to a control line RST, and a drain terminal 94d is connected to a power source line P92 (power source voltage VREF). A second terminal 952 of the current source 905 is connected to a power source line P93 (source voltage VREF).
FIG. 17 is a timing chart showing operations of Related Art 1, which shows voltages of the control lines RST, RSEL and the nodes N1, N2 shown in FIG. 16. Solid lines and broken lines of the nodes N1 and N2 show the voltages where the light amount of LuxA and LuxB are irradiated, respectively.
The operation is mainly divided into three periods. In a reset period from time t0 to t1, the transistor 904 comes to be in an electrically connected state because the potential of the control line RST changes from VSS to VDD, the both-end voltages of the photodiode 902 and the storage capacitance 903 are reset, and the potential of the node N1 turns to VREF.
In an integrating period from time t1 to t2, the electric charges of the photodiode 902 and the storage capacitance 903 are decreased according to the light amount irradiated to the photodiode 902, and the voltage of the node N1 is decreased.
In a readout period from time t2 to t3, the potential of the control line RSEL is increased from VSS to VREF. Thus, the potential of the node N1 is also increased to be equal to or higher than the threshold voltage of the transistor 901, and the potential of the node N2 is increased.
From the perspective of the gate-source voltage of the transistor 901 as the amplifier circuit, the following can be said. That is, in the reset period from time t0 to t1, the voltage of VREF is applied to the gate terminal 91g. However, the voltage of the source terminal 91s is also VREF, so that no voltage is applied between the gate and the source.
In the integrating period from time t1 to t2, a photoelectric current is flown to the photodiode 902 according to the irradiated light amount. As the electric charges accumulated in the photodiode 902 and the storage capacitance 903 decrease, the gate voltage of the transistor 901 changes to the decreasing direction. Thus, the polarity of the voltage between the gate and the source of the transistor 901 turns to negative.
In the readout period from time t2 to t3, the gate voltage of the transistor 901 is increased as the potential of the control line RSEL is increased, and the voltage between the gate and the source is increased in positive polarity. Thereafter, the parasitic capacitance of the output wiring DATA is charged by the transistor 901, and the potential of the node N2 reaches the voltage lower than the gate voltage of the transistor 901 by the amount of the threshold voltage. That is, a positive voltage is not applied continuously at all times between the gate and the source of the amplifier circuit TFT using the APS technique but a negative voltage may be applied or the extent of the voltage may be changed arbitrarily. The similar technique is also disclosed in Japanese Unexamined Patent Application Publication 2009-540628 (Patent Document 6 (FIG. 8, FIG. 9)).
However, with Related Art 1, the signals outputted from each of the pixels 900 come to be delayed when the gate potential of the transistor 901 constituting the amplifier circuit is controlled. This causes such a critical issue that high-speed operations cannot be executed. The reasons thereof will be described hereinafter.
In the circuit structure of FIG. 16, the source terminal 91s of the transistor 901 functioning as the amplifier circuit is directly connected to the output wiring DATA. In a case where the voltage of the node N1 that is the gate voltage of the transistor 901 is smaller than the value acquired by adding the threshold voltage to the source voltage of the transistor 901, the transistor 901 is in an off state but the capacitance between the gate and the source of the transistor 901 becomes the parasitic capacitance of the output wiring DATA.
In a case where a-Si or an amorphous oxide semiconductor is used as the semiconductor material of the transistor 901, TFT of an inverted staggered structure as shown in FIG. 18 is employed for the transistor 901. In the transistor 901, a gate electrode 911 is formed on a substrate, a semiconductor layer 930 is formed thereon via a gate insulating film 920, and a drain electrode 941 and a source electrode 942 are formed at both ends of the semiconductor layer 930, respectively.
The reason for employing the inverted staggered structure for the transistor 901 is because the TFT manufacturing steps can be simplified compared to the cases of employing other structures (e.g., a case of employing a planar structure). However, with the inverted staggered structure, the two-dimensionally overlapping area of the source electrode 942 and the gate electrode 911 becomes large, so that the capacitance between the gate and the source becomes larger as well. That is, the parasitic capacitance of the output wiring DATA becomes large.
Further, the transistor 901 operates as a source follower, and the voltage between the gate and the source becomes smaller as the output voltage of the source follower approaches the target voltage (an ideal output voltage corresponding to an input voltage). This means that the drain current of the transistor 901 decreases abruptly as the output voltage approaches the target voltage.
Normally, in order to improve the response speed of the source follower, used is a method which increases the channel width of the transistor 901. However, with the circuit structure disclosed herein, the parasitic capacitance of the output wiring DATA becomes increased when the channel width of the transistor 901 is increased. Thus, the response speed cannot be improved. This issue becomes more conspicuous as the number of pixels connected to a single output wiring DATA becomes greater. That is, it is a critical issue for the image sensor having a great number of pixels.
It is therefore an exemplary object of the present invention to provide an image sensor suited for a radiation image capturing device with which: the fluctuation in the characteristic of a signal amplifying transistor formed by a thin film semiconductor disposed at each pixel is suppressed; no issue in terms of the reliability is generated; the S/N ratio is high; and high-speed operations can be done.